The present invention relates to an information processing system, and more particularly to a virtual machine system having an address translation function.
In an information processing system which uses a virtual memory system, it is necessary to translate a virtual address for the information processing system to access data or instruction on a main storage, to an absolute address on the main storage.
A prior art technique on general specification for the translation of the virtual address to the absolute address is described in the IBM publications, "IBM System 370 Principles of Operations" (GA-22-7000), "IBM System 370 Extended Architecture Principles of Operation" (SA 22-7085), and "IBM Enterprise System Architecture/370 Principles of Operation" (SA 22-7200).
Recently, an information processing system called a virtual machine system has been realized and commonly used. As shown in FIG. 1, the virtual machine system configures the information processing system such that a plurality of virtual machines are generated under one real machine. A virtual machine control program (VMCP) runs on the real machine and an operating system (OS) on the plurality of virtual machines is operated under the control of the VMCP.
As shown in FIG. 2, the OS which runs on the real machine (which is the VMCP and called a level-1 OS) prepares an address translation table by the level-1 OS, and the OS which runs on the virtual machine (level-2 OS) runs on a virtual address space (level-1 virtual main storage) on the level-1 OS.
Accordingly, in the prior art virtual machine system, in order to translate the level-2 OS virtual address to the level-1 OS absolute address, it is necessary to translate the address by using two address translation tables, one prepared by the level-1 OS and the other prepared by the level-2 OS. In the course of the address translation, as shown in FIG. 3, up to eight times of accessing to the address translation tables is usually required. Thus, when the address translation is to be achieved by a hardware logic, it increases a cost. Accordingly, the address translation is usually carried out by a microprogram called a virtual machine assist (VMA) or a shadow translation table which is a set of address translation table prepared by the level-1 OS by combining translation information of two sets of address translation tables as shown in FIG. 2.
In the method which uses the shadow translation table, the translation from the level-2 virtual address to the level-1 absolute address is quassi-performed by hardware like the translation from the level-1 virtual address to the level-1 absolute address so that the performance overhead in the address translation is reduced. However, there still remains an overhead in preparing the shadow translation table by the VMCP which is the level-1 OS. This overhead brings a non-negligible process performance reduction to the system.
A method for eliminating this overhead is the realization of two-step address translation by hardware. An address translation process therefor is shown in FIG. 3 and general specification thereof is described in the IBM publication "IBM System/370 Extended Architecture Interpretive Execution" (SA 22-7095). Technique on specific procedures to realize the specification is disclosed in JP-A-57-212680 and JP-A-62-19949.
In order to support the two-step address translation by the hardware, VMCP's of the level-1 OS and the level-2 OS are prepared as the virtual machine, and a level-3 OS is realized as a virtual machine under the control of the VMCP which is the level-2 OS. In this case, as shown in FIG. 4, the address translation is carried out by using three address translation tables. It is possible to fully support such a three-level address translation by hardware, but 32 times of accessing to the address translation tables or the main storage is required per address translation. This is a non-negligible problem with the performance and it is not practical because of the increase of the hardware cost.
A prior art technique on the specific method for implementing the three-step address translation is disclosed in U.S. Pat. No. 4,792,895.
In the disclosed prior art, the VMCP explained in connection with FIG. 4 is used as the level-1 OS and the level-2 OS, the level-3 OS is generated as a virtual machine under the control of the VMCP which is the level-2 OS, and a shadow translation table is prepared by combining the level-1 OS address translation table and the level-2 OS address translation table.
The method of converting the three-step address translation to the two-step address translation by using the shadow translation table can reduce the overehead caused in the address translation as described above, but there still remains an overhead for preparing the shadow translation table or maintenance, which is yet not negligible.